Non-volatile memory (NVM) arrays, such as but not limited to, electrically erasable, programmable read only memory (EEPROM) arrays, are utilized for storage of data. Typically, the data stored therein may be changed, either by programming or erasing multiple times over the lifetime of the array. In NVM arrays, each cell may be individually programmed. In EEPROM arrays, each cell may be individually erased, as opposed to erasable, programmable read only memory (EPROM or FLASH arrays, wherein groups of cells, instead of individual cells, may be erased.
Reference is now made to FIG. 1, which illustrates a typical NVM array 10. The NVM array 10 may typically comprise rows and columns of memory cells 12 connected to word lines 14 (rows of the array) and bit lines 16 (columns). The memory cells 12 may store one or more bits (e.g., single bit cells or dual bit cells). The description follows for dual bit cells having a left-side bit 18 and a right-side bit 19 in the sense of FIG. 1.
Each memory cell may be connected to one word line and at least one bit line. Depending on the array architecture, another terminal of the memory cell may be connected to another bit line as shown in FIG. 1, in which case one of the bit lines is called the drain line and the other is the source line. Other connections are also possible in other array architectures, such as connecting to a common source ground. Reading, programming (also referred to as writing) or erasing bits of cells requires application of certain voltages to the word line and bit lines.
Programming a bit of a memory cell increases the threshold voltage Vt thereof. Programming typically comprises application of a positive voltage to the word line and drain line connected to the bit to be programmed, with the source grounded. Reading the bit typically comprises application of a much lower positive voltage to the word line than that used for writing, and a positive voltage to the drain, with the source grounded. Erasing the cell decreases the threshold voltage Vt. Erasing typically comprises application of a negative voltage to the word line and a positive voltage to the drain line, with the source floating.
Program-word-line voltages are generally applied only to the word line to which the bit to be programmed is connected. All other word lines in the array are typically grounded in order to avoid various problems, such as but not limited to, unwanted programming of bits on other word lines and unwanted disturbs to other bits in the array. Accordingly, a single write operation may be used to program a byte of data by programming the data into bits that are connected to a common word line.
A user wishing to write data to a NVM array may typically write the data to a cache memory, such as but not limited to, a static random access memory (SRAM). The cache memory routes or “addresses” the data to the appropriate bits in the NVM array. As mentioned above, a single write operation may program a byte of data to bits connected to a common word line. Therefore, in an efficient write operation, a byte address would comprise both the left-side bits 18 and the right-side bits 19 of the cells on a common word line, as indicated by reference numeral 20 in FIG. 1.
Unlike a write (i.e., program) operation, in a read operation it may be possible to use more than one word line at a time. This may be possible due to the lower word line voltages used in a read operation, which may be sufficiently low so as not to cause unwanted disturbs or programming of other bits in the array. There is an incentive to use more than one word line at a time, because it would speed up the read operation. In order to read bits on multiple word lines at the same, the bits should be connected to common bit lines. Accordingly, the left-side bits 18 of a given cell would belong to a different byte address than the right-side bits 19 of the same cell, as indicated by reference numeral 22 in FIG. 1.
In light of the foregoing explanation, in an effort to speed up the reading operation, a conflict may exist in the byte addresses of an NVM array. In the write operation, the byte address may comprise both the left-side bits 18 and the right-side bits 19 of the cells on a common word line. However, in the read operation, the byte address may comprise only the left-side bits 18 over multiple word lines (or the right-side bits 19 over multiple word lines). This poses a problem in addressing the bytes for both write and read operations.